HCPL-3150 Datasheet, PDF (13/15 Pages) Agilent(Hewlett-Packard) – 0.5 Amp Output Current IGBT Gate Drive Optocoupler

θ_LD = 439°C/W
T_JE
T_JD
θ_LC = 391°C/W
θ_DC = 119°C/W
T_C
θ_CA = 83°C/W*
T_A
Figure 28. Thermal Model.
T_JE = LED junction temperature
T_JD = detector IC junction temperature
T_C = case temperature measured at the center of the package bottom
θ_LC = LED-to-case thermal resistance
θ_LD = LED-to-detector thermal resistance
θ_DC = detector-to-case thermal resistance
θ_CA = case-to-ambient thermal resistance
∗θ_CA will depend on the board design and the placement of the part.
CMR with the LED On
(CMR_H)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum I_FLH of
5 mA to achieve 15 kV/µs CMR.
CMR with the LED Off
(CMR_L)
A high CMR LED drive circuit
must keep the LED off
(V_F ≤ V_F(OFF)) during common
mode transients. For example,
during a -dV_CM/dt transient in
Figure 31, the current flowing
through C_LEDP also flows through
the R_SAT and V_SAT of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than V_F(OFF), the
LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dV_CM/dt
transient, since all the current
flowing through C_LEDN must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMR_L
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150
output is in the high state and the
supply voltage drops below the
HCPL-3150 V_UVLO- threshold
(9.5 <V_UVLO- <12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6 µs.
When the HCPL-3150 output is in
the low state and the supply
voltage rises above the HCPL-
3150 V_UVLO+ threshold
(11.0 < V_UVLO+ < 13.5), the
optocoupler will go into the high
state (assuming LED is “ON”)
with a typical delay, UVLO TURN
On Delay, of 0.8 µs.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-3150 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
1-209