HDSP-253 Datasheet, PDF (10/16 Pages) Agilent(Hewlett-Packard) – Eight Character 5 mm Smart Alphanumeric Display

10
UDC RAM and UDC Address
Register
Figure 3 shows the logic levels
needed to access the UDC RAM
and the UDC Address Register.
The UDC Address Register is
eight bits wide. The lower four
bits (D₀-D₃) are used to select one
of the 16 UDC locations. The
upper four bits (D₄-D₇) are not
used. Once the UDC address has
been stored in the UDC Address
Register, the UDC RAM can be
accessed.
To completely specify a 5 x 7
character requires eight write
cycles. One cycle is used to store
the UDC RAM address in the UDC
Address Register. Seven cycles
are used to store dot data in the
UDC RAM. Data is entered by
rows. One cycle is needed to
access each row. Figure 4 shows
the organization of a UDC
character assuming the symbol to
be stored is an “F.” A₀-A₂ are used
to select the row to be accessed
and D₀-D₄ are used to transmit
the row dot data. The upper three
bits (D₅-D₇) are ignored. D₀ (least
significant bit) corresponds to the
right most column of the 5 x 7
matrix and D₄ (most significant
bit) corresponds to the left most
column of the 5 x 7 matrix.
Figure 3. Logic Levels to Access a UDC Character.
Flash RAM
Figure 5 shows the logic levels
needed to access the Flash RAM.
The Flash RAM has one bit
associated with each location of
the Character RAM. The Flash
input is used to select the Flash
RAM. Address lines A₃-A₄ are
ignored. Address lines A₀-A₂ are
used to select the location in the
Flash RAM to store the attribute.
D₀ is used to store or remove the
flash attribute. D₀ = “1” stores
the attribute and D₀ = “0”
removes the attribute.
Figure 4. Data to Load ""F'' into the UDC RAM.
When the attribute is enabled
through bit 3 of the Control Word
and a “1” is stored in the Flash
RAM, the corresponding
character will flash at approxi-
mately 2 Hz. The actual rate is
dependent on the clock frequency.
For an external clock the flash
rate can be calculated by dividing
the clock frequency by 28,672.