RF70 Datasheet, PDF (19/25 Pages) –

RF70 V1.0
The packet is repeatedly retransmitted as
long as CE is high. TX_REUSE is set by the
SPI command REUSE_TX_PL, and is reset
by the SPI command W_TX_PAYLOAD
or FLUSH TX
TX_FULL
5
0
R
TX FIFO full flag
1: TX FIFO full; 0: Available locations in
TX FIFO
TX FIFO empty flag.
TX_EMPTY
4
1
R
1: TX FIFO empty
0: Data in TX FIFO
Reserved
3:2
00
R/W Only '00' allowed
RX FIFO full flag
RX_FULL
1
0
R
1: RX FIFO full
0: Available locations in RX FIFO
RX FIFO empty flag
RX_EMPTY
0
1
R
1: RX FIFO empty
0: Data in RX FIFO
N/A
ACK_PLD
255:0
X
W
Written by separate SPI command ACK
packet payload to data pipe number PPP
given in SPI command
Used in RX mode only
Maximum three ACK packet payloads can
be pending. Payloads with same PPP are
handled first in first out.
Written by separate SPI command TX data
N/A
TX_PLD
255:0
X
W
pay-load register 1 - 32 bytes. This register
is implemented as a FIFO with three levels.
Used in TX mode only
N/A
RX_PLD
255:0
X
R
Read by separate SPI command
RX data payload register. 1 - 32 bytes.
This register is implemented as a FIFO with
three levels.
All RX channels share the same FIFO.
1C
DYNPD
Reserved
DPL_P5
DPL_P4
DPL_P3
DPL_P2
DPL_P1
DPL_P0
Enable dynamic payload length
7:6
0
R/W
Only „00‟ allowed
5
0
R/W Enable dynamic payload length data pipe 5.
(Requires EN_DPL and ENAA_P5)
4
0
R/W Enable dynamic payload length data pipe 4.
(Requires EN_DPL and ENAA_P4)
3
0
R/W Enable dynamic payload length data pipe 3.
(Requires EN_DPL and ENAA_P3)
2
0
R/W Enable dynamic payload length data pipe 2.
(Requires EN_DPL and ENAA_P2)
1
0
R/W Enable dynamic payload length data pipe 1.
(Requires EN_DPL and ENAA_P1)
0
0
R/W Enable dynamic payload length data pipe 0.
(Requires EN_DPL and ENAA_P0)
1D
FEATURE
R/W Feature Register
Reserved
7:3
0
R/W
Only „00000‟ allowed
EN_DPL
2
0
R/W Enables Dynamic Payload Length
EN_ACK_PAY 1
0
R/W Enables Payload with ACK
EN_DYN_ACK 0
0
R/W
Enables the W_TX_PAYLOAD_NOACK
command
Note: Don’t write reserved registers and registers at other addresses in register bank 0
Table 4 Register Bank 0
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