RF70 Datasheet, PDF (17/25 Pages) –

RF70 V1.0
1: Register bank 1
RX_DR
6
0
R/W Data Ready RX FIFO interrupt
Asserted when new data arrives RX FIFO
Write 1 to clear bit.
TX_DS
5
0
R/W Data Sent TX FIFO interrupt
Asserted when packet transmitted on TX. If
AUTO_ACK is activated, this bit is set high
only when ACK is received.
Write 1 to clear bit.
Maximum number of TX retransmits
MAX_RT
4
0
R/W interrupt
Write 1 to clear bit. If MAX_RT is asserted
it must be cleared to enable further
communication.
RX_P_NO
3:1
111
R
Data pipe number for the payload available
for reading from RX_FIFO
000-101: Data Pipe Number
110: Not used
111: RX FIFO Empty
TX_FULL
0
0
R
TX FIFO full flag.
1: TX FIFO full
0: Available locations in TX FIFO
08
OBSERVE_TX
Transmit observe register
PLOS_CNT
7:4
0000 R
Count lost packets. The counter is overflow
protected to 15, and discontinues at max
until reset. The counter is reset by writing to
RF_CH.
Count retransmitted packets. The counter is
ARC_CNT
3:0
0000 R
reset when transmission of a new packet
starts.
09
CD
Reserved
7:1
000000 R
CD
0
0
R
Carrier Detect
0A
RX_ADDR_P0
39:0
0xE7E7E R/W
7E7E7
Receive address data pipe 0. 5 Bytes
maximum length. (LSB byte is written first.
Write the number of bytes defined by
SETUP_AW)
0B
RX_ADDR_P1
39:0
0xC2C2C R/W
2C2C2
Receive address data pipe 1. 5 Bytes
maximum length. (LSB byte is written first.
Write the number of bytes defined by
SETUP_AW)
0C
RX_ADDR_P2 7:0
0xC3 R/W Receive address data pipe 2. Only LSB
MSB bytes is equal to RX_ADDR_P1[39:8]
0D
RX_ADDR_P3 7:0
0xC4 R/W Receive address data pipe 3. Only LSB
MSB bytes is equal to RX_ADDR_P1[39:8]
0E
RX_ADDR_P4 7:0
0xC5 R/W Receive address data pipe 4. Only LSB.
MSB bytes is equal to RX_ADDR_P1[39:8]
0F
RX_ADDR_P5 7:0
0xC6
R/W
Receive address data pipe 5. Only LSB.
MSB bytes is equal to RX_ADDR_P1[39:8]
Transmit address. Used for a PTX device
only.
10
TX_ADDR
39:0
0xE7E7E R/W
(LSB byte is written first)
7E7E7
Set RX_ADDR_P0 equal to this address to
handle automatic acknowledge if this is a
PTX device
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