RF70 Datasheet, PDF (15/25 Pages) –

RF70 V1.0
7 Register Map
There are two register banks, which can be toggled by SPI command “ACTIVATE” followed with
0x53 byte, and bank status can be read from Bank0_REG7 [7].
7.1 Register Bank 0
Address
(Hex)
Mnemonic
Bit
00
CONFIG
Reserved
7
MASK_RX_DR 6
MASK_TX_DS 5
MASK_MAX_RT 4
EN_CRC
3
CRCO
2
PWR_UP
1
PRIM_RX
0
01
EN_AA
Reserved
7:6
ENAA_P5
5
ENAA_P4
4
ENAA_P3
3
ENAA_P2
2
ENAA_P1
1
ENAA_P0
0
02
EN_RXADDR
Reserved
7:6
ERX_P5
5
ERX_P4
4
ERX_P3
3
ERX_P2
2
ERX_P1
1
ERX_P0
0
Reset
Value
0
0
0
0
1
0
0
0
Type
Description
Configuration Register
R/W Only '0' allowed
R/W Mask interrupt caused by RX_DR
1: Interrupt not reflected on the IRQ pin
0: Reflect RX_DR as active low interrupt
on the IRQ pin
R/W Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ pin
0: Reflect TX_DS as active low interrupt on
the IRQ pin
R/W Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ pin
0: Reflect MAX_RT as active low interrupt
on the IRQ pin
R/W
Enable CRC. Forced high if one of the bits
in the EN_AA is high
R/W CRC encoding scheme
'0' - 1 byte
'1' - 2 bytes
R/W 1: POWER UP, 0:POWER DOWN
R/W RX/TX control,
1: PRX, 0: PTX
Enable „Auto Acknowledgment‟ Function
00
R/W Only '00' allowed
1
R/W Enable auto acknowledgement data pipe 5
1
R/W Enable auto acknowledgement data pipe 4
1
R/W Enable auto acknowledgement data pipe 3
1
R/W Enable auto acknowledgement data pipe 2
1
R/W Enable auto acknowledgement data pipe 1
1
R/W Enable auto acknowledgement data pipe 0
Enabled RX Addresses
00
R/W Only '00' allowed
0
R/W Enable data pipe 5.
0
R/W Enable data pipe 4.
0
R/W Enable data pipe 3.
0
R/W Enable data pipe 2.
1
R/W Enable data pipe 1.
1
R/W Enable data pipe 0.
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