HMC5983-DEM Datasheet, PDF (22/28 Pages) Honeywell Accelerometers – 3-Axis Digital Compass IC

HMC5983
I²C COMMUNICATION PROTOCOL
If selected, the HMC5983 communicates via a two-wire I²C bus system as a slave device. The HMC5983 uses a simple
protocol with the interface protocol defined by the I²C bus specification, and by this document. The data rate is at the
standard-mode 100kbps, 400kbps, or 3400kbps rates as defined in the I²C Bus Specifications. The bus bit format is an 8-
bit Data/Address send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII
characters or binary data to the HMC5983 slave, and binary data returned. Negative binary values will be in two’s
complement form. The default (factory) HMC5983 8-bit slave address is 0x3C for write operations, or 0x3D for read
operations.
The HMC5983 Serial Clock (SCL) and Serial Data (SDA) lines require resistive pull-ups (Rp) between the master device
(usually a host microprocessor) and the HMC5983. Pull-up resistance values of about 2.2K to 10K ohms are
recommended with a nominal VDDIO voltage. Other resistor values may be used as defined in the I²C Bus Specifications
that can be tied to VDDIO.
The SCL and SDA lines in this bus specification may be connected to multiple devices. The bus can be a single master to
multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device, which is
responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I²C ’s
unique 7-bit address. After each 8-bit transfer, the master device generates a 9^th clock pulse, and releases the SDA line.
The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leave
the SDA high to negative acknowledge (NACK).
Per the I²C spec, all transitions in the SDA line must occur when SCL is low. This requirement leads to two unique
conditions on the bus associated with the SDA transitions when SCL is high. Master device pulling the SDA line low while
the SCL line is high indicates the Start (S) condition, and the Stop (P) condition is when the SDA line is pulled high while
the SCL line is high. The I²C protocol also allows for the Restart condition in which the master device issues a second
start condition without issuing a stop.
All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The
address byte contains the slave address; the upper 7 bits (bits7-1), and the Least Significant bit (LSb). The LSb of the
address byte designates if the operation is a read (LSb=1) or a write (LSb=0). At the 9^th clock pulse, the receiving slave
device will issue the ACK (or NACK). Following these bus events, the master will send data bytes for a write operation, or
the slave will clock out data with a read operation. All bus transactions are terminated with the master issuing a stop
sequence.
I²C bus control can be implemented with either hardware logic or in software. Typical hardware designs will release the
SDA and SCL lines as appropriate to allow the slave device to manipulate these lines. In a software implementation, care
must be taken to perform these tasks in code.
SPI COMMUNICATION PROTOCOL
If selected, the HMC5983 communicates via a 3-wire or 4-wire SPI bus as a slave device. The SPI allows writing and
reading the registers of the device.
The standard Serial Interface interacts with the outside world with 4 wires: CS, SCK, SDI and SDO that correspond to
commonly used notations SS, SCK, MOSI and MISO, respectively.
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