HI-6138 Datasheet, PDF (203/254 Pages) Holt Integrated Circuits – 40 MHz SPI Host Interface

HI-6138
Bit No.
Mnemonic
R/W Reset Function
Description of the RAM BIST “PATTERN” test selected when register
bits RBSEL2:0 = 001:
Note: Test read /write accesses to addresses 0x0000 - 0x0051 involve 82
RAM locations not accessible to the host. These accesses do not affect the
host-accessible registers, overlaying the same address range.
1. Write 0x0000 to all RAM locations, 0x0000 through 0x1FFF.
2. Repeat the following sequence for each RAM location from 0x00000
through 0x1FFF:
a. Read and verify 0x0000
b. Write then read and verify 0x5555
c. Write then read and verify 0xAAAA
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f. Write then read and verify 0x0F0F
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
i. Write then read and verify 0xFF00
j. Write 0x0000 then increment RAM address and go to step (a)
13,12,11 RBSEL2:0 R/W 0 _{3. Write 0xFFFF to all RAM locations, 0x0000 through 0x1FFF}
(continued)
4. Repeat the following sequence for each RAM location from 0x00000
through 0x1FFF:
a. Read and verify 0xFFFF
b. Write then read and verify 0x5555
c. Write then read and verify 0xAAAA
d. Write then read and verify 0x3333
e. Write then read and verify 0xCCCC
f. Write then read and verify 0x0F0F
g. Write then read and verify 0xF0F0
h. Write then read and verify 0x00FF
i. Write then read and verify 0xFF00
j. Write 0xFFFFthen increment RAM address and go to step (a)
5. Write each cell’s memory address into each RAM location from 0x00020
to 0x1FFF.
6. Read each memory location from 0x00000 to 0x1FFF and verify it con-
tains its address.
7. Write 1s complement of each cell’s memory address, into each RAM
location (same addr range).
8. Read each memory location and verify it contains the 1s complement of
its address.
RAM BIST Start.
Writing logic 1 to this bit initiates the RAM BIST test selected by register
bits RBSEL2:0. The RBSTRT bit can only be set if the TEST input pin
10 RBSTRT R/W 0 _{is high and if register bit 15 is already asserted. This bit is automatically}
cleared upon test completion. Register bits 9:8 indicate pass / fail test
result. The user must reload MAP register with 0x28 before each register
read that polls result bits 9:8.
HOLT INTEGRATED CIRCUITS
203