HI-6138 Datasheet, PDF (156/254 Pages) Holt Integrated Circuits – 40 MHz SPI Host Interface

HI-6138
Bit No. Mnemonic R/W Reset Function
14 IWA
Interrupt When Accessed.
If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IWA bit is
high, assertion of this bit enables interrupt generation at each instance of
R/W 0 _{a valid mode code command. Upon completion of command processing,}
when IWA interrupts are enabled, an IWA interrupt is entered in the “Remote
Terminal (RT) Pending Interrupt Register (0x0009)”, the INT output pin is
asserted, and the interrupt is registered in the Interrupt Log.
13 IBR
Interrupt Broadcast Received.
If the “Remote Terminal (RT) Interrupt Enable Register (0x0012)” IBR bit is
high, assertion of this bit enables interrupt generation at each instance of a
valid broadcast transmit mode code command. Upon completion of command
R/W 0 ^{processing, when IBR interrupts are enabled, an IBR interrupt is entered in}
the “Remote Terminal (RT) Pending Interrupt Register (0x0009)”, the INT
output pin is asserted, and the interrupt is registered in the Interrupt Log.
This bit has no function if the BCSTINV bit is high in the “Remote Terminal
Configuration Register (0x0017)”. In this case, commands to RT address 31
are not recognized as valid by the device.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the “Remote Terminal MIL-STD-1553
12 MKBUSY R/W 0 ^{Status Word Bits Register (0x001A)”. See that register description for addi-}
tional information. When Busy is asserted, mode data words are not transmit-
ted with MC16-MC31, and the DPB bit does not toggle after message com-
pletion. The MKBUSY bit is not heeded if set in the Control Word for mode
code command MC8 “reset remote terminal”. For this command only, Busy is
inhibited for the status response transmitted before the reset process begins.
11 DBAC
Descriptor Block Accessed.
R
0
SR = 0
Internal device logic asserts the DBAC bit upon completion of message pro-
cessing. The host may poll this bit to detect mode command activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
10 DPB
Data Pointer B.
This status bit is maintained by the device and only applies for mode
commands using ping-pong buffer mode. This bit indicates the buffer to be
used for the next occurring mode command. When the DPB bit is logic 0,
the next message will use Data Pointer A; when DPB is logic 1, the next
message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted
R
0
SR = 0
after each error-free message completion. To also ensure the DPB bit
is not altered after illegal commands or messages ending with Busy
status, the DPBTOFF bit should be set in the “Extended Configuration
Register (0x004D)” on page 43. This ensures unsuccessful messages
are not stored in the data buffer and are overwritten by subsequent
successful messages. (see also “Ping-Pong Enable / Disable Handshake”
on page 168). The DBP bit is reset to logic 0 by MR master reset or SRST
software reset; therefore the first message received after either reset will use
Buffer A. This bit is “don’t care” for indexed single-buffer mode.
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