HI-6138 Datasheet, PDF (129/254 Pages) Holt Integrated Circuits – 40 MHz SPI Host Interface

HI-6138
Bit No. Mnemonic
3
BMTF
2
RTAPF
1
EELF
0
TFBINH
R/W Reset Function
BIST Memory Test Fail.
R
0
This bit is set if error occurs during built-in self-test for device Random
Access Memory (RAM) (see Section “21.2.1. Self-Test Control Register
(0x0028)” on page 201).
RT Address Parity Fail.
This bit is asserted when “Remote Terminal Operational Status Register
(0x0018)” bits 15:10 reflect parity error. After MR master reset, bits 15:10
R
0 _{in the RT’s Operational Status Register reflect input pin states, but will}
be overwritten if subsequent auto-initialization is performed (if AUTOEN
pin is high) and the initialization EEPROM contains different data for RT
Operational Status Register bits 15:10.
Auto-Initialization EEPROM Load Fail.
This bit only applies when auto-initialization is enabled (AUTOEN input
R
0
pin state equals 1). This bit is set if, after MR master reset, failure
occurs when copying serial EEPROM to registers and RAM. When this
occurs, bit 0 or bit 1 will be set in the “Master Status and Reset Register
(0x0001)” to indicate type of failure.
This bit is set when the Terminal Flag status bit is disabled while fulfilling
R
0
an “inhibit terminal flag bit” mode code command (MC6). This bit is reset
if terminal flag status bit disablement is cancelled later by an “override
inhibit terminal flag bit” mode code command (MC7).
15.11. Remote Terminal Alternate Built-In Test (BIT) Word Register (0x001F)
MSB
Register Value
LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW
Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset.
It is not affected by assertion of RTRESET remote terminal software reset in the “Master Status and Reset Register
(0x0001)”. If the ALTBITW option bit in the “Remote Terminal Configuration Register (0x0017)” equals one when a
valid “transmit BIT word” mode command (MC19) is received, the current value in this register is transmitted as the
mode data word in the terminal response. The value is also copied to the assigned data buffer for MC19, after mode
command fulfillment.
15.12. Remote Terminal Time Tag Counter Register (0x0049)
MSB
Register Value
LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R
Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This register is read-only and is cleared after MR pin Master Reset or assertion of RTRESET remote terminal software
reset in the “Master Status and Reset Register (0x0001)”. Reads to this register address return the current value of the
free running 16-bit Time Tag counter. Counter resolution is programmed by the TTCK2:0 bits in the “Time Tag Counter
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