HT67F60A Datasheet, PDF (99/242 Pages) Holtek Semiconductor Inc – TinyPowerTM A/D Flash MCU with LCD & EEPROM

HT67F60A/HT67F70A
TinyPower^TM A/D Flash MCU with LCD & EEPROM
Bit 6~4
Bit 3
Bit 2~0
CTnCK2~CTnCK0: Select CTMn Counter clock
000: fSYS/4
001: fSYS
010: fH/16
011: fH/64
100: fTBC
101: Reserved
110: CTCKn rising edge clock
111: CTCKn falling edge clock
These three bits are used to select the clock source for the CTMn. Selecting the
Reserved clock input will effectively disable the internal counter. The external pin
clock source can be chosen to be active on the rising or falling edge. The clock source
fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which
can be found in the oscillator section.
CTnON: CTMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the CTMn. Setting the bit high enables
the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero
will stop the counter from counting and turn off the CTMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the CTMn is in
the Compare Match Output Mode then the CTMn output pin will be reset to its initial
condition, as specified by the CTnOC bit, when the CTnON bit changes from low to
high.
CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter bit9~bit7
000: 1024 CTMn clocks
001: 128 CTMn clocks
010: 256 CTMn clocks
011: 384 CTMn clocks
100: 512 CTMn clocks
101: 640 CTMn clocks
110: 768 CTMn clocks
111: 896 CTMn clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which
are then compared with the internal counter’s highest three bits. The result of this
comparison can be selected to clear the internal counter if the CTnCCLR bit is set to
zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest three counter bits, the compare values exist in 128 clock cycle multiples.
Clearing all three bits to zero is in effect allowing the counter to overflow at its
maximum value.
Rev. 1.10
99
December 01, 2016