HT67F60A Datasheet, PDF (180/242 Pages) Holtek Semiconductor Inc – TinyPowerTM A/D Flash MCU with LCD & EEPROM

HT67F60A/HT67F70A
TinyPower^TM A/D Flash MCU with LCD & EEPROM
SPIA Communication
After the SPIA interface is enabled by setting the SPIAEN bit high, then in the Master Mode, when
data is written to the SPIAD register, transmission/reception will begin simultaneously. When the
data transfer is complete, the SATRF flag will be set automatically, but must be cleared using the
application program. In the Slave Mode, when the clock signal from the master has been received,
any data in the SPIAD register will be transmitted and any data on the SDIA pin will be shifted into
the SPIAD registers.
The master should output a SCSA signal to enable the slave device before a clock signal is provided.
The slave data to be transferred should be well prepared at the appropriate moment relative to the
SCSA signal depending upon the configurations of the SACKPOLB bit and SACKEG bit. The
accompanying timing diagram shows the relationship between the slave data and SCSA signal for
various configurations of the SACKPOLB and SACKEG bits. The SPIA will continue to function if
the SPIA clock source is active.
Rev. 1.10
180
December 01, 2016