BC68F2123 Datasheet, PDF (82/117 Pages) Holtek Semiconductor Inc – Sub-1GHz OOK/FSK TX Soc 1K Flash MCU

BC68F2123
Sub-1GHz OOK/FSK TX Soc 1K Flash MCU
Single Pulse Output Mode
To select this mode, the required bit pairs, PT1M1 and PT1M0 should be set to 10 respectively and
also the corresponding PT1IO1 and PT1IO0 bits should be set to 11 respectively. The Single Pulse
Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.
The trigger for the pulse output leading edge is a low to high transition of the PT1ON bit, which
can be implemented using the application program. However in the Single Pulse Output Mode, the
PT1ON bit can also be made to automatically change from low to high using the external PTCK1
pin, which will in turn initiate the Single Pulse output. When the PT1ON bit transitions to a high
level, the counter will start running and the pulse leading edge will be generated. The PT1ON bit
should remain high when the pulse is in its active state. The generated pulse trailing edge will be
generated when the PT1ON bit is cleared to zero, which can be implemented using the application
program or when a compare match occurs from Comparator A.
However a compare match from Comparator A will also automatically clear the PT1ON bit and thus
generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control
the pulse width. A compare match from Comparator A will also generate TM interrupts. The counter
can only be reset back to zero when the PT1ON bit changes from low to high when the counter
restarts. In the Single Pulse Mode CCRP is not used. The PT1CCLR bit is also not used.
S/W Command
SET“PT1ON”
or
PTCK1 Pin
Transition
CCRA
Leading Edge
PT1ON bit
0à1
CCRA
Trailing Edge
PT1ON bit
1à0
S/W Command
CLR“PT1ON”
or
CCRA Compare
Match
PTP1 Output Pin
Pulse Width = CCRA Value
Single Pulse Generation
Rev. 1.00
82
January 11, 2017