BC68F2123 Datasheet, PDF (60/117 Pages) Holtek Semiconductor Inc – Sub-1GHz OOK/FSK TX Soc 1K Flash MCU

BC68F2123
Sub-1GHz OOK/FSK TX Soc 1K Flash MCU
Bit 3
Bit 2
Bit 1
Bit 0
In the Compare Match Output Mode, the ST0IO1~ST0IO0 bits determine how the
STM0 output pin changes state when a compare match occurs from the Comparator A.
The TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the ST0IO1~ST0IO0
bits are both zero, then no change will take place on the output. The initial value of
the TM output pin should be setup using the ST0OC bit. Note that the output level
requested by the ST0IO1~ST0IO0 bits must be different from the initial value setup
using the ST0OC bit otherwise no change will occur on the TM output pin when a
compare match occurs. After the TM output pin changes state, it can be reset to its
initial level by changing the level of the ST0ON bit from low to high.
In the PWM Output Mode, the ST0IO1 and ST0IO0 bits determine how the TM output
pin changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values of
the ST0IO1 and ST0IO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the ST0IO1 and ST0IO0 bits are changed when the TM is
running.
ST0OC: STM0 Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Output Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the STM output pin. Its operation depends upon
whether STM is being used in the Compare Match Output Mode or in the PWM
Output Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/
Counter Mode. In the Compare Match Output Mode it determines the logic level
of the STM output pin before a compare match occurs. In the PWM output Mode it
determines if the PWM signal is active high or active low. In the Single Pulse Output
Mode it determines the logic level of the STM output pin when the ST0ON bit
changes from low to high.
ST0POL: STM0 STP0 Output polarity Control
0: Non-inverted
1: Inverted
This bit controls the polarity of the STP0 output pin. When the bit is set high the STM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
ST0DPX: STM0 PWM period/duty Control
0: CCRP – period; CCRA – duty
1: CCRP – duty; CCRA – period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
ST0CCLR: Select STM0 Counter clear condition
0: STM0 Comparator P match
1: STM0 Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the ST0CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The ST0CCLR bit is not
used in the PWM output mode, Single Pulse or Input Capture Mode.
Rev. 1.00
60
January 11, 2017