HT66F4360 Datasheet, PDF (115/263 Pages) Holtek Semiconductor Inc – Smart Card Reader Flash MCU

HT66F4360/HT66F4370/HT66F4390
Smart Card Reader Flash MCU
STMRP Register
Bit
Name
R/W
POR
7
STRP7
R/W
0
6
STRP6
R/W
0
5
STRP5
R/W
0
4
STRP4
R/W
0
3
STRP3
R/W
0
2
STRP2
R/W
0
1
STRP1
R/W
0
0
STRP0
R/W
0
Bit 7~0
STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit
15~bit 8
Comparator P match period =
0: 65536 STM clocks
1~255: (1~255) × 256 STM clocks
These eight bits are used to setup the value on the internal CCRP 8-bit register, which
are then compared with the internal counter’s highest eight bits. The result of this
comparison can be selected to clear the internal counter if the STCCLR bit is set to
zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP
values will reset the internal counter. As the CCRP bits are only compared with the
highest eight counter bits, the compare values exist in 256 clock cycle multiples.
Clearing all eight bits to zero is in effect allowing the counter to overflow at its
maximum value.
Standard Type TM Operation Modes
The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the STM1 and STM0 bits in the STMC1 register.
Compare Match Output Mode
To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when
a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the
counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and
Comparator P respectively, will both be generated.
If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the STMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output
Mode, the CCRA can not be set to “0”.
As the name of the mode suggests, after a comparison is made, the STM output pin, will change
state. The STM output pin condition however only changes state when a STMAF interrupt request
flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the STM
output pin. The way in which the STM output pin changes state are determined by the condition of
the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the
STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the STM output pin, which is setup after
the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and
STIO0 bits are zero then no pin change will take place.
Rev. 1.30
115
December 15, 2016