HD66100F Datasheet, PDF (9/17 Pages) Hitachi Semiconductor – LCD Driver with 80-Channel Outputs

HD66100F
Primary Operations
Shifting Data
The input data DI shifts at the fall of CL2 and the data delayed 80 bits by the shift register is output from
the DO terminal. The output of DO changes synchronously with the rise of CL2. This operation is
completely unaffected by the latch clock CL1.
Latching Data
The data of the shift register is latched at the negative edge of the latch clock CL1. Thus, the outputs Y1–
Y80 change synchronously with the fall of CL1.
Switching Data Shift Direction
When the shift direction switching signal SHL is connected with GND, the data D80, immediately before
the negative edge of CL1, is output from the output terminal Y1. When SHL is connected with V_CC, it is
output from Y80.
Shift clock CL2
Input data DI
Output data DO
Figure 5 Timing of Receiving and Outputting Data
Shift clock CL2
Latch clock CL1
Outputs Y1–Y80
Figure 6 Timing of Latching Data
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