HD66100F Datasheet, PDF (16/17 Pages) Hitachi Semiconductor – LCD Driver with 80-Channel Outputs

HD66100F
Timing Chart of Input Waveforms
Shift clock CL2
1
2
3
78
79
80
......
Input data DI
SEG80 SEG79 SEG78 ^{. . . . . . . .} SEG3 SEG2 SEG1
Latch clock CL1
Figure 13 Timing Chart of Input Waveforms
Notes: 1. Input square waves of 50% duty cycle (about 30–500 Hz) to M. The frequency depends on the
specifications of LCD panels.
2. The drive waveforms corresponding to the new displayed data are output at the fall of CL1.
Therefore, when the alternating signal M and CL1 do not fall synchronously, DC elements are
produced on the LCD drive waveforms. These DC elements may shorten the life span of the
LCD, if the displayed data frequently changes (e.g. display of hours, minutes, and seconds of a
clock). To avoid this, make CL1 fall synchronously with the one edge of M.
3. In this example, the CMOS inverter is used as a COM signal driver in consideration of the
large display area. (The load capacitance on COM is large because it is common to all the
displayed segments.)
Usually, one of the HD66100F outputs can be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in that case.
COM
LCD
Y2–Y80
Y1
SHL
HD66100F
Figure 14 Example of Connection
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