HD74CDC857 Datasheet, PDF (8/12 Pages) Hitachi Semiconductor – 3.3/2.5-V Phase-lock Loop Clock Driver

HD74CDC857
Electrical Characteristics
Item
Symbol Min
Typ ^*1 Max Unit Test Conditions
Input clamp CLK, CLK
V_IK
voltage
FBIN, FBIN, G
—
—
–1.2 V
I_I = –18 mA, V_DDQ = 2.3 V
Output voltage
V_OH
V_CC–0.2 —
—
V
I_OH = –100 µA, V_CC = 2.3 to 2.7 V
1.95 —
—
I_OH = –8 mA, V_CC = 2.3 V
1.70 —
—
I_OH = –16 mA, V_CC = 2.3 V
V_OL
—
—
0.2
I_OL = 100 µA, V_CC = 2.3 to 2.7 V
—
—
0.35
I_OL = 8 mA, V_CC = 2.3 V
—
—
0.55
I_OL = 16 mA, V_CC = 2.3 V
Input current
I_I
—
—
±10
µA V_I = 0 V to 2.7 V, V_DDQ = 2.7 V
Input capacitance
C_I
—
—
4
pF
Note: 1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
Switching Characteristics
Item
Symbol Min
Typ
Cycle to cycle jitter
–100 —
Phase error time
t_{(phase error)} –150
—
Output skew
t_{sk (o)}
—
—
Differential clock skew
t_{sk (diff)}
–100
—
Duty cycle
45
—
Output impedance
Clock frequency
Z_O
—
25
f _CLK
100
—
130
—
Max
100
150
200
100
55
—
150 ^*1
150 ^*1
Slew rate
1.2
—
—
Stabilization time
—
—
0.1
Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99.
Unit Test Conditions
ps See figure 2
ps See figure 2, 3, 4
ps See figure 2
ps See figure 2
% See figure 2
Ω See figure 2
MHz See figure 2, AV_CC = 2.5±0.2 V
See figure 2, AV_CC = 2.5±0.2 V
or AV_CC = 3.3±0.3 V
V/ns See figure 2
ms See figure 2, 3
8