HD74CDC857 Datasheet, PDF (4/12 Pages) Hitachi Semiconductor – 3.3/2.5-V Phase-lock Loop Clock Driver

HD74CDC857
Recommended Operating Conditions
Item
Symbol Min
Typ
Max
Unit Conditions
Supply voltage
Output supply voltage
DC input signal voltage ^*1
AV_CC (1) 2.3
—
AV_CC (2) 3.0
—
V_DDQ
2.3
—
–0.3
—
High level input voltage
V_IHD
1.7
—
Low level input voltage
V_ILD
—
—
High level input voltage
V_IHG
1.7
—
Low level input voltage
V_ILG
–0.3
—
Differential input signal voltage ^*2 V_ID
0.36
—
0.7
—
Differential cross point voltage ^*3
0.5×V_DDQ —
–0.35
2.7
V
3.6
2.7
V
V_DDQ+0.3 V
—
V
0.8
V
V_DDQ+0.3 V
0.7
V
V_DDQ+0.6 V
V_DDQ+0.6
0.5×V_DDQ V
+0.35
f_CLK = 100 to 150 MHz
f_CLK = 130 to 150 MHz
All pins
G input pin
G input pin
DC
AC
Reference voltage ^*4
Output current
Input slew rate
V_ref
1.15
1.25
1.35
V Vref = 0.5 × V_DDQ
I _OH
–7
—
–30
mA
I _OL
7
—
30
SR
1
—
—
V/ns
Operating temperature
T_a
0
—
70
°C
Notes: Unused inputs must be held high or low to prevent them from floating.
Feedback inputs (FBIN, FBIN) may float when the device is in low power mode.
1. DC input signal voltage specifies the allowable dc execution of differential input.
2. Differential input signal voltage specifies the differential voltage |VTR–VCP| required for
switching, where VTR is the true input level and VCP is the complementary input level.
3. Differential cross point voltage is expected to track variations of V_DDQ and is the voltage at which
the differential signals must be crossing. (See figure1-1)
4. V_ref is the reference DC level, when using single clock input. When CLK (pin#13) is single ended
input, CLK (pin#14) must be set V_ref . (See figure1-2)
4