HD404369 Datasheet, PDF (77/115 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer

HD404369 Series
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.
• Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0.
External clock mode
STS wait state
(octal counter = 000,
transmit clock disabled)
00 MCU reset
SMR write 04
01 STS instruction
06 SMR write (IFS ^← 1)
Transmit clock wait state
(octal counter = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS ^← 1)
Transfer state
(octal counter ≠ 000)
Internal clock mode
SMR write
18
STS wait state
(octal counter = 000,
transmit clock disabled)
10 MCU reset
Continuous clock output state
(PMRA 0, 1 = 0, 0)
SMR write 14
11 STS instruction
Transmit clock 17
Transmit clock wait state
(octal counter = 000)
12 Transmit clock
15
STS instruction (IFS ← 1)
13 8 transmit clocks
16 SMR write (IFS←1)
Transfer state
(octal counter ≠ 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 59 Serial Interface State Transitions
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