HD74CDCF2509B Datasheet, PDF (7/11 Pages) Hitachi Semiconductor – 140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver

HD74CDCF2509B
Switching Characteristics (C_L = 25 pF, Ta = 0 to 85°C)
Item
Phase error time
Symbol
t _pe
V_CC = 3.3 V±0.3 V
Min Typ Max
–125 —
125
Unit
ps
Between output pins skew ^*1 t_{sk (O)}
—
—
150 ps
From (Input) To (Output)
66 MHz <
CLKIN↑
≤ 133 MHz
Any Y or
FBOUT
FBIN↑
Any Y or
FBOUT
Cycle to cycle jitter
–75 —
75
ps
F (clkin =
133 MHz)
Any Y or
FBOUT
Duty cycle
45
—
55
%
F (clkin =
Any Y or
66 to 133 MHz) FBOUT
Slew rate
5.0 —
1.0 volts/ns
Any Y or
FBOUT
Analog power supply
rejection
(DC to 10 MHz)
Vapsr ^*2 100 —
—
mV_P–P
AV_CC
Notes:
The specifications for parameters in this table are applicable only after any appropriate
stabilization time has elapsed.
1. The t_sk(O) specification is only valid for equal loading of all outputs.
2. This parameter is characterized but not tested.
Timing requirements
Item
Symbol Min
Max
Unit
Test Conditions
Input clock frequency
Input clock duty cycle
f _clock
50
40
140
MHz
60
%
Stabilization time ^*1
—
1
ms
After power up
Note:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its
reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay and skew parameters given in the switching characteristics table are not
applicable.
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