HD66130T Datasheet, PDF (7/16 Pages) Hitachi Semiconductor – 320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display

Operation Timing
(1) 4-bit capture mode (1 line, 640 dots)
Line
HD66130T
CL2
D0
to
D3
CL1
EIO2
(No. 1)
EIO2
(No. 2)
Y1–Y320
12
d4 d8
d1 d5
79 80 81 82
d316 d320
d313 d317
159 160 161
Data capture period
for IC (No. 1)
Data capture period for IC
(No. 2)
BS = GND (4-bit capture mode)
During the data standby state when the data capture operation enable signal is low (SHL = GND: EIO1),
the next data capture clock (CL2) cancels the standby state. The 4-bit data is captured at the fall of CL2.
When 316 bits are captured, the enable signal becomes the GND level (SHL = GND: EIO2). When 320
bits are captured, the operation automatically stops (the standby state is entered). The second IC is then
activated when pin EIO2 is connected to pin EIO1 of the second IC.
Data output changes at the fall of CL1.
During SHL = GND, captured data d1 and d320 are output to Y1 and Y320, respectively. During SHL =
Vcc, data d1 and d320 are output to Y320 and Y1, respectively.
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