HD66130T Datasheet, PDF (4/16 Pages) Hitachi Semiconductor – 320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display

HD66130T
Pin Functions
Class
Power
supply
Control
signal
Pin
Pin
Symbol Number Name I/O Functions
V_CC
343
GND1 324
GND2 340
V_CC
— V_CC–GND: Power supply for logic.
GND
V0L, R
VML, R
V1L, R
345, 322 V0L, R
346, 321 VML, R
344, 323 V1L, R
Input Liquid crystal drive level power supply
V0
VM
V1
CL1 327
Clock 1 Input Latch signal of display data: A liquid crystal drive signal
corresponding to display data is output at the fall of CL1.
CL2 328
Clock 2 Input Capture signal of display data: Display data is captured
at the fall of CL2.
M
326
M
Input A.C. signal of liquid crystal drive output
D0 to D7 336 to
329
DATA 0 Input
to
DATA 7
Display data Liquid crystal drive output Liquid crystal display
1 (Vcc level) Selected level
ON
0 (GND level) Not-selected level
OFF
SHL 339
EIO1 338
Shift Left Input Control signal for inverting the order of data output
(see the following page)
Enable I/O
IO1
SHL
GND
EI/O1
Enable input
EI/O2
Enable output
Vcc
Enable output
Enable input
EIO2 325
DISP 337
BS
341
Enable I/O
IO2
Enable input: The enable input of the first IC is
connected to the GND and another is connected to the
enable output of the second IC.
Enable output: Connected to the enable input of the
second IC at cascade output.
Disp off Input Grounding DISP sets liquid crystal drive output Y1–Y320
to the VM level.
Bus
Input Switches the number of input bits for the display data.
Select
Vcc 8-bit input mode
GND 4-bit input mode (Captures data from D0–D3. At this
time, connect D4–D7 to the GND.)
MODE 342
MODE
Input Switches the number of input bits for the display data.
Vcc 320 output mode
GND 240 output mode (Y41–Y280 are valid output. The
other 80 pins output the not-selected-level signals
synchronized every time; release these pins.)
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