HD66130T Datasheet, PDF (15/16 Pages) Hitachi Semiconductor – 320-channel Low-voltage Segment Driver for Dot-Matrix STN Liquid Crystal Display

HD66130T
AC Characteristics 1 (V_CC = 2.5 to 4.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)
Item
Clock cycle time
Clock high pulse width 1
Clock low pulse width 1
Clock high pulse width 2
Clock setup time
Clock hold time
Clock rise time
Clock fall time
Data setup time
Data hold time
M setup time
M hold time
Output delay time 1
Symbol
t _CYC
t _CWH2
t _CWL2
t _CWH1
t _SCL
t _HCL
t_r
t_f
t _DS
t _DH
t _MS
t _MH
t _pd1
Pins
Min
CL2
152
CL2
65
CL2
65
CL1
65
CL1, CL2
80
CL1, CL2
80
CL1, CL2
—
CL1, CL2
—
D0 to D7, CL2 50
D0 to D7, CL2 50
M, CL1
20
M, CL1
20
CL1, Y1 to Y320 —
Max
Unit
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
30
ns
30
ns
—
ns
—
ns
—
ns
—
ns
1000
ns
AC Characteristics 2 (V_CC = 4.5V to 5.5V, V0–GND = 2.6 to 5.5V, Ta = –30 to +75°C)
Item
Symbol
Pins
Min
Max
Clock cycle time
t _CYC
CL2
125
Clock high pulse width 1 t_CWH2
CL2
45
Clock low pulse width 1
t _CWL2
CL2
45
Clock high pulse width 2 t_CWH1
CL1
45
Clock setup time
t _SCL
CL1, CL2
80
Clock hold time
t _HCL
CL1, CL2
80
Clock rise time
t_r
CL1, CL2
—
Clock fall time
t_f
CL1, CL2
—
Data setup time
t _DS
D0 to D7, CL2 20
Data hold time
t _DH
D0 to D7, CL2 20
M setup time
t _MS
M, CL1
20
M hold time
t _MH
M, CL1
20
Output delay time 1
t _pd1
CL1, Y1 to Y320 —
Notes: 1. A load must be 10 pF or less for EI/O connection between drivers.
—
—
—
—
—
—
20
20
—
—
—
—
1000
2. For output delay time 1 and 2, connect the load circuit shown below.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test point
100 pF
15