HM5212165F Datasheet, PDF (60/63 Pages) Hitachi Semiconductor – 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM

HM5212165F/HM5212805F-75/A60/B60
Power Down Mode
CLK
CKE
CS
,
,,^RAS
CKE Low

,
,
_
^,_
,,^{,
,

,,,
, CAS}
WE
, _BS
Address
A10=1
R: a
DQM,
DQMU/DQML
 _{DQ (input)}

DQ (output)
High-Z
t_RP
Precharge command Power down entry
 !"+

_{,45=EFNOPGAIJ@89B7H.? 
,,
,}^{ $&'08.67?@H9AIJ-If needed}
Power down cycle
Power down
mode exit
RAS-CAS delay = 3
Active Bank 0 CAS latency = 3
Burst length = 4
= V_IH or V_IL
, ^{, ,
 ,
 InitializationSequence}
CLK
CKE
CS
RAS
CAS
WE
Address
0 1 2 3 4 5 6 7 8 9 10
V_IH
valid
48 49 50 51 52 53 54 55
code
Valid
DQM,
V_IH
DQMU/DQML
DQ
High-Z
t _RP
All banks
Precharge
Auto Refresh
t _RC
t_RC
Auto Refresh
t _RSA
Mode register
Set
Bank active
If needed
60