HM5212165F Datasheet, PDF (51/63 Pages) Hitachi Semiconductor – 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM

HM5212165F/HM5212805F-75/A60/B60
HM5212165F/
HM5212805F
Parameter
-75
-A60/B60
Frequency (MHz)
133
100
t_CK (ns)
HITACHI PC/100
Symbol Symbol 7.5
10
CS to command disable
l_CDD
0
0
Power down exit to command input
l_PEC
1
1
Burst stop to output valid data hold
(CAS latency = 2)
l_BSR
1
1
(CAS latency = 3)
l_BSR
2
2
Burst stop to output high impedance
(CAS latency = 2)
l_BSH
2
2
(CAS latency = 3)
l_BSH
3
3
Burst stop to write data ignore
l_BSW
0
0
Notes: 1. l_RCD to l_RRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
51