HM5212165F Datasheet, PDF (1/63 Pages) Hitachi Semiconductor – 128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM

HM5212165F-75/A60/B60
HM5212805F-75/A60/B60
128M LVTTL interface SDRAM
133 MHz/100 MHz
2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank
PC/133, PC/100 SDRAM
ADE-203-1048A (Z)
Rev. 1.0
Jan. 31, 2000
Description
The Hitachi HM5212165F is a 128-Mbit SDRAM organized as 2097152-word × 16-bit × 4-bank. The
Hitachi HM5212805F is a 128-Mbit SDRAM organized as 4194304-word × 8-bit × 4-bank. All inputs and
outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
• 3.3 V power supply
• Clock frequency: 133 MHz/100 MHz (max)
• LVTTL interface
• Single pulsed RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
 Sequential (BL = 1/2/4/8/full page)
 Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Byte control by DQM : DQM (HM5212805F)
: DQMU/DQML (HM5212165F)
• Refresh cycles: 4096 refresh cycles/64 ms