HB28C048A6 Datasheet, PDF (6/66 Pages) Hitachi Semiconductor – FLASH ATA Card

HB28C048/032/016A6
Signal name
Direction Pin No.
Description
-CSEL
I
56
(PC Card Memory mode)
This signal is not used.
-CSEL
(PC Card I/O mode)
-CSEL
(True IDE mode)
This signal is used to configure this device as a
Master or a Slave when configured in the True IDE
mode. When this pin is grounded, this device is
configured as a Master. When the pin is open, this
device is configured as a Slave.
D15 to D0
I/O
(PC Card Memory mode)
41, 40, 39, 38, Data bus is D15 to D0. D0 is the LSB of the even byte
37, 66, 65, 64, 6, of the word. D8 is the LSB of the odd byte of the
5, 4, 3, 2, 32, 31, word.
30
D15 to D0
(PC Card I/O mode)
D15 to D0
(True IDE mode)
GND
—
(PC Card Memory mode)
1, 34, 35, 68
Ground
GND
(PC Card I/O mode)
GND
(True IDE mode)
-INPACK
O
60
(PC Card Memory mode)
This signal is not used and should not be connected
at the host.
-INPACK
(PC Card I/O mode)
Input Acknowledge
This signal is asserted low by this card when the card
is selected and responding to an I/O read cycle at the
address that is on the address bus during -CE and
-IORD are low. This signal is used for the input data
buffer control.
-INPACK
(True IDE mode)
This signal is not used and should not be connected
at the host.
-IORD
I
44
(PC Card Memory mode)
This signal is not used.
-IORD
(PC Card I/O mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until I/O
card interface setting up.
-IORD
(True IDE mode)
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until True
IDE interface setting up.
6