HM5216805 Datasheet, PDF (56/60 Pages) Hitachi Semiconductor – 16 M LVTTL Interface SDRAM 100 MHz/83 MHz 1-Mword ´ 8-bit ´ 2-bank/2-Mword ´ 4-bit ´ 2-bank

HM5216805 Series, HM5216405 Series
Power Down Mode
CLK
CKE
CKE Low
CS
RAS
CAS
WE
A11(BS)
Address
DQMU
/DQML
I/O(input)
I/O(output)
A10=1
t_RP
Precharge command Power down entry
If needed
Power Up Sequence
CLK
CKE
01234567
V_IH
8

^{R: a}
High-Z
Power down cycle
Power down
RAS-CAS delay=3
mode exit
Active Bank 0
CAS latency=2
Burst length=4
= V_IH or V_IL
9 10
48 49 50 51 52 53 54 55
CS
RAS
CAS
WE
Address
DQMU
/DQML
I/O
Valld
code
Valld
V_IH
High-Z
t_RP
t_RC
t_RC
t_RSA
All banks Auto Refresh
Auto Refresh
Mode register Bank active
Precharge
Set
If needed
56