HM5216805 Datasheet, PDF (1/60 Pages) Hitachi Semiconductor – 16 M LVTTL Interface SDRAM 100 MHz/83 MHz 1-Mword ´ 8-bit ´ 2-bank/2-Mword ´ 4-bit ´ 2-bank

HM5216805 Series,
HM5216405 Series
16 M LVTTL Interface SDRAM
100 MHz/83 MHz
1-Mword × 8-bit × 2-bank/2-Mword × 4-bit × 2-bank
ADE-203-304E (Z)
Rev. 5.0
November 1, 1997
Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216805 Series,
HM5216405 Series are offered in 2 banks for improved performance.
Features
• 3.3V Power supply
• Clock frequency: 100 MHz/83 MHz (max)
• LVTTL interface
• Single pulsed RAS
• 2 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
 Sequential (BL = 1/2/4/8/full page)
 Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 1/2/3
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
 Auto refresh
 Self refresh (L-version)