HM5216805 Datasheet, PDF (16/60 Pages) Hitachi Semiconductor – 16 M LVTTL Interface SDRAM 100 MHz/83 MHz 1-Mword ´ 8-bit ´ 2-bank/2-Mword ´ 4-bit ´ 2-bank

HM5216805 Series, HM5216405 Series
Current state CS RAS CAS WE Address
Command
Operation
Write with auto- H × × × ×
precharge
DESL
Continue burst to end and
precharge
L HHH×
NOP
Continue burst to end and
precharge
L HHL ×
BST
ILLEGAL
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA
ACTV
Other bank active
ILLEGAL on same bank^*3
L L H L BA, A10
PRE, PALL
ILLEGAL
L L L H×
REF, SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Refresh (auto- H × × × ×
refresh)
DESL
Enter IDLE after t_RC
L HHH×
NOP
Enter IDLE after t_RC
L HHL ×
BST
Enter IDLE after t_RC
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA
ACTV
ILLEGAL
L L H L BA, A10
PRE, PALL
ILLEGAL
L L L H×
REF, SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
Notes: 1. H: V_IH. L: V_IL. ×: V_IH or V_IL.
The other combinations are inhibit.
2. An interval of t_DPL is required between the final valid data input and the precharge command.
3. If t_RRD is not satisfied, this operation is illegal.
From [PRECHARGE]
To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the
IDLE state after t_RP has elapsed from the completion of precharge.
From [IDLE]
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
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