2SK1862 Datasheet, PDF (4/6 Pages) Hitachi Semiconductor – Silicon N-Channel MOS FET

2SK1862, 2SK1863
Power vs. Temperature Derating
30
20
10
0
50
100
150
Case Temperature Tc (°C)
Maximum Safe Operation Area
30
10
3
1
0.3
OilnipmetihtreaisdtiaobrnyeaRis^DS
((oTncD) _{=C2O5pP°CeWr)a=tio1n0}
1 _ms
ms ₍₁
Shot)
0.1
0.03
1
Ta = 25°C
3 10
2SK1862
2SK1863
30 100 300 1000
Drain to Source Voltage V_DS (V)
Normalized Transient Thermal Impedance vs. Pulse Width
3
1.0 ^{D = 1}
0.5
0.3
0.2
0.1
0.1
0.05
0.02
0.03
0.01
10 µ
1 ^{shot Pulse}
0.01
100 µ
1m
10 m
Pulse Width PW (S)
Tc = 25°C
θ ch – c(t) = ^γ s(t) ^. θ ch – c
θ ch – c = 5.0°C / W, Tc = 25°C
P DM
D
=
PW
T
PW
T
100 m
1
10
4