HD44780U Datasheet, PDF (31/59 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal Display Controller/Driver

HD44780U
Write Data to CG or DDRAM
Write data to CG or DDRAM writes 8-bit binary data DDDDDDDD to CG or DDRAM.
To write into CG or DDRAM is determined by the previous specification of the CGRAM or DDRAM
address setting. After a write, the address is automatically incremented or decremented by 1 according to
the entry mode. The entry mode also determines the display shift.
Read Data from CG or DDRAM
Read data from CG or DDRAM reads 8-bit binary data DDDDDDDD from CG or DDRAM.
The previous designation determines whether CG or DDRAM is to be read. Before entering this read
instruction, either CGRAM or DDRAM address set instruction must be executed. If not executed, the first
read data will be invalid. When serially executing read instructions, the next address data is normally read
from the second read. The address set instructions need not be executed just before this read instruction
when shifting the cursor by the cursor shift instruction (when reading out DDRAM). The operation of the
cursor shift instruction is the same as the set DDRAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1. However, display shift
is not executed regardless of the entry mode.
Note:
The address counter (AC) is automatically incremented or decremented by 1 after the write
instructions to CGRAM or DDRAM are executed. The RAM data selected by the AC cannot be
read out at this time even if read instructions are executed. Therefore, to correctly read data,
execute either the address set instruction or cursor shift instruction (only with DDRAM), then just
before reading the desired data, execute the read instruction from the second time the read
instruction is sent.
Write data to
CG or DDRAM
Read data from
CG or DDRAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1 0DDDDDDDD
Higher
order bits
Lower
order bits
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code
1 1DDDDDDDD
Higher
order bits
Lower
order bits
Figure 14 Instruction (3)
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