HD44780U Datasheet, PDF (25/59 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal Display Controller/Driver

HD44780U
Table 6 Instructions (cont)
Code
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
Write data 1 0 Write data
to CG or
DDRAM
Writes data into DDRAM or
CGRAM.
Execution Time
(max) (when f_cp or
f_OSC is 270 kHz)
37 µs
t_ADD = 4 µs*
Read data 1 1 Read data
from CG or
DDRAM
I/D = 1:
I/D = 0:
S = 1:
S/C = 1:
S/C = 0:
R/L = 1:
R/L = 0:
DL = 1:
N = 1:
F = 1:
BF = 1:
BF = 0:
Increment
Decrement
Accompanies display shift
Display shift
Cursor move
Shift to the right
Shift to the left
8 bits, DL = 0: 4 bits
2 lines, N = 0: 1 line
5 × 10 dots, F = 0: 5 × 8 dots
Internally operating
Instructions acceptable
Reads data from DDRAM or 37 µs
CGRAM.
t_ADD = 4 µs*
DDRAM: Display data RAM ^{Execution time}
CGRAM: Character generator
RAM
ACG: CGRAM address
ADD: DDRAM address
changes when
frequency changes
Example:
When f_cp or f_OSC is
250 kHz,
(corresponds to cursor
address)
AC: Address counter used for
37
µs
×
270
250
=
40
µs
both DD and CGRAM
addresses
Note: — indicates no effect.
* After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter
is incremented or decremented by 1. The RAM address counter is updated after the busy flag
turns off. In Figure 10, t_ADD is the time elapsed after the busy flag turns off until the address
counter is updated.
Busy signal
(DB7 pin)
Busy state
Address counter
(DB0 to DB6 pins)
A
t _ADD
Note: t _ADD depends on the operation frequency
t _ADD = 1.5/(f _cp or f _OSC ) seconds
Figure 10 Address Counter Update
A+1
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