HD44780U Datasheet, PDF (24/59 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal Display Controller/Driver

HD44780U
Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-
incrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data
write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform
concurrently with display data write, the user can minimize system development time with maximum
programming efficiency.
When an instruction is being executed for internal operation, no instruction other than the busy flag/address
read instruction can be executed.
Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before
sending another instruction from the MPU.
Note:
Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the
MPU to the HD44780U. If an instruction is sent without checking the busy flag, the time between
the first instruction and next instruction will take much longer than the instruction time itself. Refer
to Table 6 for the list of each instruc-tion execution time.
Table 6 Instructions
Instruction RS
Clear
0
display
Return
0
home
Entry
0
mode set
Display 0
on/off
control
Cursor or 0
display
shift
Function 0
set
Set
0
CGRAM
address
Set
0
DDRAM
address
Read busy 0
flag &
address
Code
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
0 0 0 0 0 0 0 0 1 Clears entire display and
sets DDRAM address 0 in
address counter.
Execution Time
(max) (when f_cp or
f_OSC is 270 kHz)
0 0 0 0 0 0 0 1 — Sets DDRAM address 0 in 1.52 ms
address counter. Also
returns display from being
shifted to original position.
DDRAM contents remain
unchanged.
0 0 0 0 0 0 1 I/D S Sets cursor move direction 37 µs
and specifies display shift.
These operations are
performed during data write
and read.
0 0 0 0 0 1 D C B Sets entire display (D) on/off, 37 µs
cursor on/off (C), and
blinking of cursor position
character (B).
0 0 0 0 1 S/C R/L — — Moves cursor and shifts
display without changing
DDRAM contents.
37 µs
0 0 0 1 DL N F — — Sets interface data length 37 µs
(DL), number of display lines
(N), and character font (F).
0 0 1 ACG ACG ACG ACG ACG ACG Sets CGRAM address.
37 µs
CGRAM data is sent and
received after this setting.
01
ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address.
DDRAM data is sent and
received after this setting.
37 µs
1 BF AC AC AC AC AC AC AC Reads busy flag (BF)
0 µs
indicating internal operation
is being performed and
reads address counter
contents.
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