HD404356 Datasheet, PDF (21/100 Pages) Hitachi Semiconductor – 4-bit HMCS400-Series microcomputer

HD404358 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE
Interrupt Enabled/Disabled
0
Disabled
1
Enabled
External Interrupts (INT₀, INT₁): Two external interrupt signals.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to INT₀ and INT₁, as listed in table 5.
Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)
IF0, IF1
0
1
Interrupt Request
No
Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)
IM0, IM1
0
1
Interrupt Request
Enabled
Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA
0
1
Interrupt Request
No
Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.
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