CD4051B Datasheet, PDF (7/15 Pages) Texas Instruments – CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion

CD4051B, CD4052B, CD4053B
Electrical Specifications
TEST CONDITIONS
PARAMETER
V_IS (V)
Total Harmonic Distortion, THD 2 (Note 3)
V_DD (V)
5
R_L (kΩ)
10
3 (Note 3)
10
5 (Note 3)
15
V_EE = V_SS, f_IS = 1kHz Sine Wave
-40dB Feedthrough Frequency
(All Channels OFF)
5 (Note 3)
10
1
V_EE = V_SS,
20Log ^V--_V---^O-_I--_S-^S-- = –40dB
-40dB Signal Crosstalk
Frequency
5 (Note 3)
10
1
V_EE = V_SS,
20Log -^V-_V---^O-_I--_S-^S-- = –40dB
V_OS at Common OUT/IN
CD4053
CD4052
CD4051
V_OS at Any Channel
Between Any 2 Channels
Between Sections,
CD4052 Only
Measured on Common
Measured on Any Chan-
nel
Between Any Two
Sections, CD4053
Only
In Pin 2, Out Pin 14
In Pin 15, Out Pin 14
Address-or-Inhibit-to-Signal
-
10
10
Crosstalk
(Note 4)
V_EE = 0, V_SS = 0, t_r, t_f = 20ns, V_CC
= V_DD - V_SS (Square Wave)
NOTES:
3. Peak-to-Peak voltage symmetrical about
4. Both ends of channel.
-^V----^D----^D-----₂^–-----V----^E----^E--
LIMITS
TYP
0.3
0.2
0.12
8
10
12
8
3
6
10
2.5
6
65
65
UNITS
%
%
%
%
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV_PEAK
mV_PEAK
Typical Performance Curves
600
V_DD - V_EE = 5V
500
400
300
T_A = 125^oC
200
T_A = 25^oC
T_A = -55^oC
100
0
-4 -3 -2 -1
0
1
2
3
4
5
V_IS, INPUT SIGNAL VOLTAGE (V)
FIGURE 1. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
300
V_DD - V_EE = 10V
250
200
T_A = 125^oC
150
T_A = 25^oC
100
T_A = -55^oC
50
0
-10 -7.5 -5 -2.5 0
2.5
5
7.5 10
V_IS, INPUT SIGNAL VOLTAGE (V)
FIGURE 2. CHANNEL ON RESISTANCE vs INPUT SIGNAL
VOLTAGE (ALL TYPES)
7