CD4051B Datasheet, PDF (15/15 Pages) Texas Instruments – CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion

CD4051B, CD4052B, CD4053B
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
H
E
-B-
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45^o
-C-
α
e
A1
C
B
0.10(0.004)
0.25(0.010) M C A M B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN
MAX
MIN
MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B
0.013 0.020
0.33
0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.3859 0.3937 9.80 10.00
3
E
0.1497 0.1574 3.80
4.00
4
e
0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L
0.016 0.050
0.40
1.27
6
N
16
16
7
α
0^o
8^o
0^o
8^o
-
Rev. 0 12/93
15