HC-55564 Datasheet, PDF (4/9 Pages) Harris Corporation – Continuously Variable Slope Delta-Modulator (CVSD)

Timing Waveforms
SAMPLING CLOCK
HC-55564
FZ/APT
DEC/ENC
DIGITAL NRZ IN
1
0
1
t_DS
0
DIGITAL NRZ OUT
t_DS: DATA SET UP TIME 100ns TYPICAL
0
1
1
FIGURE 2. CVSD TIMING DIAGRAM
Interface Circuit for HC-55564 CVSD (DIP Pin Numbers Shown)
AUDIO SOURCE
R_C
INPUT
LEVEL ADJUST
R_A, R_B, C_A
OPTIONAL
C_A
R_A
5V
-5V
0.1µ
TP3040
1
2
3
4
R_{B 5}
VF_X1+
VF_X1-
GS_X
VF_R0
PWRI
6
PWR0+
VF_X0 ¹⁶
VF_RI ¹⁰
9
8 ^VCC
V_BB
CLK0 ¹⁴
PDN ¹³
11
GNDA _CLK ^GNDD
0.1µ 15 12
HC-55564
AUDIO OUT
0.1µ
0.1µ
R_D (NOTE)
EXTERNAL
5 _AIN
3 _AOUT
1
V_DD
0.1µ
4
AGC
D_OUT ¹⁴
D_IN ¹²
FZ ¹³
APT ¹¹
10
E/D
CONTROL
8 _{DIGITAL ANALOG} 2
GND
GND
CLK
9
(TO DATA I/F)
(FROM DATA I/F)
EXTERNAL
CONTROL
÷n
CLK GEN
NOTE: R_D = 100kΩ to 1MΩ
CVSD Hookup for Evaluation
The circuit in Figure 3 is sufficient to evaluate the voice qual-
ity of the CVSD, since when encoding, the feedback signal at
the audio output pin is the reconstructed audio input signal.
CVSD design considerations are as follows:
1. Care should be taken in layout to maintain isolation
between analog and digital signal paths for proper noise
consideration.
2. Power supply decoupling is necessary as close to the
device as possible. A 0.1µF should be sufficient.
3. Ground, then power, must be present before any input sig-
nals are applied to the CVSD. Failure to observe this may
cause a latchup condition which may be destructive.
Latchup may be removed by cycling the power off/on. A
power-up reset circuit may be used that strobes Force
Zero (Pin 13) during power-up as follows:
4. Analog (signal) ground (Pin 2) should be externally tied to
Digital GND (Pin 8) and power supply ground. It is recom-
mended that the A_IN and A_OUT ground returns connect
only to Pin 2.
5. Digital inputs and outputs are compatible with standard
CMOS logic using the same supply voltage. All unused
logic inputs must be tied to the appropriate logic level for
desired operation. It is recommended that unused inputs
tied high be done so through a pull-up resistor (1kΩ to
10kΩ). TTL outputs will require 1kΩ pull-up resistors. Pins
4 and 14 will each drive CMOS logic or one low power TTL
input.
6. Since the Audio Out pins are internally DC biased to V_DD/2,
AC coupling is required. In general, a value of 0.1µF is suffi-
cient for AC coupling of the CVSD audio pins to a filter circuit.
7. The AGC output may be externally integrated to drive an
AGC pre-amp, or it could drive an LED indicator through a
buffer to indicate proper speaking volume.
V_DD
R
(13)
C
FZ
4