HC-55564 Datasheet, PDF (2/9 Pages) Harris Corporation – Continuously Variable Slope Delta-Modulator (CVSD)

HC-55564
Absolute Maximum Ratings
Thermal Information
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . .GND -0.3V to V_DD 0.3V
Maximum V_DD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175^oC
Operating Conditions
Temperature Range
HC-55564-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0^oC to 75⁰C
HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40^oC to 85⁰C
HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55^oC to 125⁰C
Operating V_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 6.0V
Thermal Resistance (Typical, Note 1)
θ_JA (^oC/W)
CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150^oC
Maximum Storage Temperature Range . . . . . . . . . . -65^oC to 150^oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300^oC
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V_DD
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BiMOSE
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Unless Otherwise Specified, typical parameters are at 25^oC, Min-Max are over operating temperature
ranges. V_DD = 5.0V, Sampling Rate = 16Kbps, AG = DG = 0V, A_IN = 1.2V_RMS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Sampling Rate
CLK Note 2
9
16
64
kbps
Supply Current
Logic ‘1’ Input
Logic ‘0’ Input
Logic ‘1’ Output
Logic ‘0’ Output
Clock Duty Cycle
I_DD
V_IH
Note 3
V_IL
Note 3
V_OH
Note 4
V_OL
Note 4
-
0.3
1.5
mA
3.5
-
-
V
-
-
1.5
V
4.0
-
-
V
-
-
0.4
V
30
-
70
%
Audio Input Voltage
Audio Output Voltage
Audio Input Impedance
Audio Output Impedance
Transfer Gain
Syllabic Filter Time Constant
Signal Estimate Filter Time
Constant
A_IN
A_OUT
Z_IN
Z_OUT
A_E-D
t_SF
t_SE
AC Coupled (Note 5)
AC Coupled (Note 6)
Note 7
Note 7
No Load, Audio In to Audio Out.
Note 8
Note 8
-
0.5
1.2
V_RMS
-
0.5
1.2
V_RMS
-
280
-
kΩ
-
150
-
kΩ
-2.0
-
+2.0
dB
-
4.0
-
ms
1.0
-
-
ms
Enc Threshold
AIN at 100Hz (Note 9), (Typ) 0.3% = 15mV_RMS
-
6
-
mV_PEAK
Minimum Step Size
MSS Note 10
-
0.1
-
%V_DD
Quieting Pattern Amplitude
V_QP
FZ = 0V or APT = 0V (Note 11)
-
10
-
mV_P-P
AGC Threshold
V_ATH
Note 12
-
0.1
-
F.S.
Clamping Threshold
V_CTH Note 13
-
0.75
-
F.S.
NOTES:
2. There is one NRZ (Non-Return Zero) data bit per clock period. Data is clocked out on the negative clock edge. Data is clocked into the
CVSD on the positive going edge (see Figure 2). Clock may be run at less than 9kbps and greater than 64kbps.
3. Logic inputs are CMOS compatible at supply voltage and are diode protected. Digital data input is NRZ at clock rate.
4. Logic outputs are CMOS compatible at supply voltage and will withstand short-circuits to V_DD or ground. Digital data output is NRZ and
changes with negative clock transitions. Each output will drive one LS TTL load.
5. Recommended voice input range for best voice performance. Should be externally AC coupled.
6. May be used for side-tone in encode mode. Should be externally AC coupled. Varies with audio input level by ±2dB.
7. Presents series impedance with audio signal. Zero signal reference is approximately V_DD/2.
8. Note that filter time constants are inversely proportional to clock rate. Both filters approximate single pole responses.
9. The minimum audio input voltage above which encoding takes place.
10. The minimum audio output voltage change that can be produced by the internal DAC.
11. Settled value, the “quieting” pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions.
12. A logic “0” will appear at the AGC output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at
V_DD/2 ±25% of V_DD.
13. The recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarters of full-
scale value, and will unclamp when it falls below this value (positive or negative).
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