HC-55564 Datasheet, PDF (3/9 Pages) Harris Corporation – Continuously Variable Slope Delta-Modulator (CVSD)

HC-55564
Pin Descriptions
PIN NUMBER
14 LEAD DIP
SYMBOL
DESCRIPTION
1
V_DD
Positive Supply Voltage. Voltage range is 4.5V to 6.0V.
2
Analog GND Analog Ground connection to D/A ladders and comparator.
3
A_OUT
Audio Out recovered from 10-bit DAC. May be used as side tone at the transmitter. Presents
approximately 150kΩ source with DC offset of V_DD/2. Within ±2dB of Audio Input. Should be ex-
ternally AC coupled.
4
AGC
Automatic Gain Control output. A logic low level will appear at this output when the recovered
signal excursion reaches one-half of full scale value. In each half cycle full scale is V_DD/2. The
mark-space ratio is proportional to the average signal level.
5
A_IN
Audio Input to comparator. Should be externally AC coupled. Presents approximately 280kΩ in
series with V_DD/2.
6, 7
NC
No internal connection is made to these pins.
8
Digital GND Logic ground. 0V reference for all logic inputs and outputs.
9
Clock
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode, the digital data is clocked
out on the negative going clock transition. The clock rate equals the data rate.
10
Encode/
A single CVSD can provide half-duplex operation. The encode or decode function is selected by the
Decode
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
11
APT
Alternate Plain Text input. Activating this input caused a digital quieting pattern to be transmitted, how-
ever; internally the CVSD is still functional and a signal is still available at the A_OUT port. Active low.
12
Digital In
Input for the received digital NRZ data.
13
FZ
Force Zero input. Activating this input resets the internal logic and forces the digital output and the
recovered audio output into the “quieting” condition. An alternating 1-0 pattern appears at the
digital output at 1/2 the clock rate. When this is decoded by a receive CVSD, a 10mV_P-P inaudible
signal appears at audio output. Active low.
14
Digital Out
Output for transmitted digital NRZ data.
NOTE:
14. No active input should be left in a “floating condition.”
Functional Diagram (DIP Pin Numbers Shown)
(1)
V_DD
(12)
DIGITAL
IN
3V TO 6V _VDD
2
(5)
A_IN
Z_IN
(2)
ANALOG
GND
(3) A_OUT
(SIDE TONE)
Z_OUT
(4) AGC OUT
(10)
ENC/DEC
(11) (13) FORCE
APT
ZERO
(9)
CLOCK
(8) _DIGITAL
GND
RESET
T _{F/F Q}
(14)
DIGITAL
OUT
COMPARATOR
D
3 BIT
SHIFT
REGISTER
10 BIT
DAC
10
RESET
STEP
SIZE
LOGIC
10
10 BIT
DAC
SIGNAL
6
DIGITAL
ESTIMATE
MODULATOR
FILTER 1msec
±1
SYLLABIC
FILTER
4ms
RESET
3