HMS1M32M8V Datasheet, PDF (8/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V

HANBit
HMS1M32M8V
opposite phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.
9. D_OUT is the read data of the new address.
10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output
should not be applied.
FUNCTIONAL DESCRIPTION
/CE
/WE
/OE
H
X*
X
L
H
H
L
H
L
L
L
X
Note: X means Don't Care
PACKAGING DIMMENSIONS
SIMM Design
3.18 mm
T Y P(2x )
MODE
Not Select
Output Disable
Read
Write
108.20 mm
6.35 mm
2.03 mm
1
1.02 mm
6.35 mm
95.25 mm
I/O PIN
High-Z
High-Z
D_OUT
D_IN
1.27 mm
SUPPLY CURRENT
l _SB, l _SB1
l_CC
l_CC
l_CC
16 mm
72
3.34 mm
0.25 mm MAX
2.54 mm
MIN
1.27
Gold : 1.04±0.10 mm
Solder : 0.914±0.10 mm
(Solder & Gold Plating Lead)
1.29 mm
HANBit Electronics Co.,Ltd.