HMS1M32M8V Datasheet, PDF (7/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V

HANBit
HMS1M32M8V
TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock )
Address
/OE
/CE
/WE
Data In
Data Out
t_AS(4)
t_WC
t_AW
t_CW(3)
t_WP(2)
High-Z
t_OHZ
t_WR(5)
t_DW
t_DH
Data Valid
t_OW
High-Z
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed)
t_WC
Address
/CE
/WE
t_AS(4)
t_AW
t_CW(3)
t_WP(2)
t_WR(5)
t_OH
Data In
Data Out
High-Z
t_WHZ(6,7)
t_DW
t_DH
Data Valid
t_OW
High-Z(8)
(10)
(9)
Notes(Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among
/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.
t_WP is measured from the beginning of write to the end of write.
3. t_CW is measured from the later of /CE going low to the end of write.
4. t_AS is measured from the address valid to the beginning of wirte.
5. t_WR is measured from the end of write to the address change. t_WR applied in case a write ends as /CE, or /WE going high.
6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of
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