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HMS1M32M8V Datasheet, PDF (6/9 Pages) Hanbit Electronics Co.,Ltd – SRAM MODULE 4Mbyte(1M x 32-Bit) 3.3V
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TIMING DIAGRAMS
HMS1M32M8V
TIMING WAVEFORM OF READ CYCLE( Address Controlled)( /CE =/OE = VIL , /WE = VIH)
tRC
Address
tAA
tOH
Data out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE ( /WE = VIH )
Address
/CE
/OE
Data Out
Vcc Supply
Current
High-Z
lCC
lSB
tRC
tAA
tCO
tLZ(4,5)
tOE
tOLZ
tPU
50%
Data Valid
tHZ(3,4,5)
tOHZ
tOH
tPD
50%
Notes (Read Cycle)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH
or VOL levels.
4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device
to device.
5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100%
tested.
6. Device is continuously selected with /CE = VIL.
7. Address valid prior to coincident with /CE transition low.
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