HMN1M8DVN Datasheet, PDF (2/9 Pages) Hanbit Electronics Co.,Ltd – Non-Volatile SRAM MODULE 8Mbit (1024k x 8bit) 40Pin - DIP, 3.3V

HANBit
HMN1M8DVN
FUNCTIONAL DESCRIPTION
The HMN1M8DVN executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A₀-A₁₉) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
eight data output drivers within t_ACC (access time) after the last address input signal is stable.
When power is valid, the HMN1M8DVN operates as a standard CMOS SRAM. During power-down and power-up cycles,
the HMN1M8DVN acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN1M8DVN is in the write mode whenever the /WE and /CE signals are in the active (low) state after address
inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle
is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle.
/WE must return to the high state for a minimum recovery time (t_WR) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in t_ODW from its falling edge.
The HMN1M8DVN provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal.
Power-down/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold V_PFD. When
V_CC falls below the V_PFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t
care” and all outputs are high impedance. As Vcc falls below approximately 2.5V, the power switching circuit connects the
lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power
switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can
resume after Vcc exceeds 3.0 volts.
BLOCK DIAGRAM
/OE
2 x 512K x 8
A0-A19
/WE
SRAM
Block
DQ0-DQ7
Power
/CE CON
/CE
Power – Fail
VCC
A19
Control
Lithium
Cell
PIN DESCRIPTION
A₀-A₁₉ : Address Input
/CE : Chip Enable
V_SS : Ground
DQ₀-DQ₇ : Data In / Data Out
/WE : Write Enable
/OE : Output Enable
V_CC: Power (+3.3V)
NC : No Connection
DU : Do not use.
URL:www.hbe.co.kr
Rev.0.0 (January/ 2003)
2
HANBit Electronics Co.,Ltd