S8865 Datasheet, PDF (4/6 Pages) Hamamatsu Corporation – Photodiode array combined with signal processing circuit chip

Photodiode array with amplifier S8865 series
I Timing chart
CLK
RESET
Video
1 2 3 4 5 14 15 16 17 18 19 20
123
tpw (RESET1)
8 CLOCKS
tpw (RESET2)
VIDEO OUTPUT PERIOD
1
2
n-1
INTEGRATION TIME
n
8 CLOCKS
Trig
EOS
tf (CLK)
tr (CLK)
tpw (CLK1)
t1
tpw (CLK2)
tpw (RESET1)
t2
tpw (RESET2)
tf (RESET)
tr (RESET)
KMPDC0154EB
Parameter
Clock pulse width
Clock pulse rise/fall times
Reset pulse width 1
Reset pulse width 2
Reset pulse rise/fall times
Clock pulse-reset pulse timing 1
Clock pulse-reset pulse timing 2
Symbol
Min.
tpw (CLK1), tpw (CLK2)
125
tr (CLK), tf (CLK)
0
tpw (RESET1)
10
tpw (RESET2)
20
tr (RESET), tf (RESET)
0
t1
-20
t2
-20
Typ.
Max.
Unit
-
12500
ns
20
30
ns
-
-
µs
-
-
µs
20
30
ns
0
20
ns
0
20
ns
1. The internal timing circuit starts operation at a fall of CLK immediately after a RESET pulse sets to Low.
2. When a fall of CLK is counted as "1 clock", the video signal at the 1st channel appears between "18.5 clocks and 20 clocks".
Then a video signal appears every 4 clocks.
3. Signal charge integration time equals the High period of a RESET pulse. However, the charge integration does not start at the
rise of a RESET pulse but starts at the 8th clock after the rise of the RESET pulse and ends at the 8th clock after the fall of the
RESET pulse. Signals integrated within this period are sequentially read out as time-series signals by the shift register
operation when the RESET pulse next changes from High to Low. The rise and fall of a RESET pulse must be synchronized
with the fall of a CLK pulse, but the rise of a RESET pulse must be set outside the video output period. One cycle of RESET
pulses cannot be set shorter than the time equal to "(video signal readout period 16.5 + 4) × N (number of pixels)" clocks.
4