S7986-01 Datasheet, PDF (3/7 Pages) Hamamatsu Corporation – CCD area image sensor Back-thinned FT-CCD for low-light-level NTSC B/W TV application

CCD area image sensor S7986-01, S7987-01
s Electrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter
Symbol Remark
Min.
Typ.
Saturation output voltage
Vsat
-
-
Fw × Sv
Vertical
30
65
Full well capacity
Fw
-
Horizontal
60
130
CCD node sensitivity
Sv
*⁴
1.5
2.0
Dark current
(MPP mode)
Readout noise
25 °C
0 °C
DS
*⁵
-
2,000
-
100
Nr
*⁶
-
150
Dynamic range (area scanning)
DR
*⁷
100
430
Spectral response range
Photo response non-uniformity
λ
-
PRNU
*⁸
-
200 to 1,100
-
-
*4: VOD=15 V, Load resistance=2.2 kΩ
*5: Dark current doubles for every 5 to 7 °C.
*6: -40 °C, operating frequency is 12 MHz.
*7: DR = Fw / Nr
*8: Measured at half of the full well capacity.
PRNU (%) = noise / signal × 100
Noise: fixed pattern noise (peak to peak)
Max.
-
-
-
-
6,000
300
300
-
-
+/-10
Unit
V
ke-
µV/e-
e-/pixel/s
e-rms
-
nm
%
s Pin connections
Pin
S7986-01
S7987-01
No. Symbol
Description
Symbol
Description
1
RD Reset drain
RD Reset drain
2
OS Output transistor source
OS Output transistor source
3
OD Output transistor drain
OD Output transistor drain
4
OG Output gate
OG Output gate
5
SG Summing gate
SG Summing gate
6
NC
NC
7
NC
NC
8
P2H CCD horizontal register clock-2
P2H CCD horizontal register clock-2
9
P1H CCD horizontal register clock-1
P1H CCD horizontal register clock-1
10 IG2H Test point (horizontal input gate-2) IG2H Test point (horizontal input gate-2)
11 IG1H Test point (horizontal input gate-1) IG1H Test point (horizontal input gate-1)
12 ISH Test point (horizontal input source) ISH Test point (horizontal input source)
13
TG Transfer gate
TG Transfer gate
14 P2VS ^{CCD vertical register clock-2}
(storage area)
P2VS ^{CCD vertical register clock-2}
(storage area)
15 P1VS ^{CCD vertical register clock-1}
(storage area)
P1VS ^{CCD vertical register clock-1}
(storage area)
16
NC
Th1 Thermistor
17
NC
Th2 Thermistor
18
NC
P- TE-cooler-
19
NC
P+ TE-cooler+
20
SS Substrate (GND)
SS Substrate (GND)
21
P2VI ^{CCD vertical register clock-2}
(image area)
P2VI ^{CCD vertical register clock-2}
(image area)
22
P1VI ^{CCD vertical register clock-1}
(image area)
P1VI ^{CCD vertical register clock-1}
(image area)
23
NC
NC
24
RG Reset gate
RG Reset gate
*9: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2VS should be applied to the TG.
Remark
Same timing as P2H
Shorted to 0 V
Shorted to 0 V
Shorted to RD
Same timing as P2VS ^*9
3