S7986-01 Datasheet, PDF (2/7 Pages) Hamamatsu Corporation – CCD area image sensor Back-thinned FT-CCD for low-light-level NTSC B/W TV application

CCD area image sensor S7986-01, S7987-01
s Absolute maximum ratings (Ta=25 °C)
Parameter
Symbol
Min.
Operating temperature
Topr
-50
Storage temperature
Tstg
-50
OD voltage
VOD
-0.5
RD voltage
VRD
-0.5
ISV voltage
VISV
-0.5
ISH voltage
VISH
-0.5
IGV voltage
VIG1V, VIG2V
-10
IGH voltage
VIG1H, VIG2H
-10
SG voltage
VSG
-10
OG voltage
VOG
-10
RG voltage
VRG
-10
TG voltage
VTG
-10
Vertical clock voltage (image area)
VP1VI, VP2VI
-10
Vertical clock voltage (storage area)
VP1VS, VP2VS
-10
Horizontal clock voltage
VP1H, VP2H
-10
s Operating conditions (MPP mode, Ta=25 °C)
Parameter
Symbol
Output transistor drain voltage
VOD
Reset drain voltage
VRD
Output gate voltage
VOG
Substrate voltage
VSS
Test point (vertical input source)
VISV
Test point (horizontal input source)
VISH
Test point (vertical input gate)
VIG1V, VIG2V
Test point (horizontal input gate)
VIG1H, VIG2H
Vertical shift register
High
VP1VIH, VP2VIH
clock voltage (Image area)
Low
VP1VIL, VP2VIL
Vertical shift register
High
VP1VSH, VP2VSH
clock voltage (Storage area)
Low
VP1VSL, VP2VSL
Horizontal shift register
High
VP1HH, VP2HH
clock voltage
Low
VP1HL, VP2HL
Summing gate voltage
High
Low
VSGH
VSGL
Reset gate voltage
High
Low
VRGH
VRGL
Transfer gate voltage
High
Low
VTGH
VTGL
Min.
12
11.5
1
-
-
-
-8
-8
4
-9
4
-9
4
-9
4
-9
4
-9
4
-9
s Electrical characteristics (Ta=25 °C)
Parameter
Symbol
Remark
Min.
Signal output frequency
fc
-
-
Reset clock frequency
frg
-
-
Vertical shift register capacitance
(Image area)
CP1VI
CP2VI
-
-
Vertical shift register capacitance
(Storage area)
CP1VS
CP2VS
-
-
Horizontal shift register capacitance CP1H, CP2H
-
-
Summing gate capacitance
CSG
-
-
Reset gate capacitance
CRG
-
-
Transfer gate capacitance
Transfer efficiency
CTG
CTE
-
-
*¹
0.99995
DC output level
Vout
*²
-
Output impedance
Zo
*²
-
Power dissipation
P
*^2, *³
-
*1: Charge transfer efficiency per pixel, measured at half of the full well capacity.
*2: VOD=15 V, Load resistance=2.2 kΩ
*3: Power dissipation of the on-chip amplifier.
Typ.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
15
12
3
0
VRD
VRD
0
0
6
-8
6
-8
6
-8
6
-8
6
-8
6
-8
Typ.
1
1
3,000 (TBD)
3,000 (TBD)
100 (TBD)
7
7
50 (TBD)
0.99999
8 (TBD)
500 (TBD)
60 (TBD)
Max.
+30
+70
+25
+18
+18
+18
+15
+15
+15
+15
+15
+15
+15
+15
+15
Max.
18
12.5
5
-
-
-
-
-
8
-7
8
-7
8
-7
8
-7
8
-7
8
-7
Max.
14
14
-
-
-
-
-
-
-
-
-
-
Unit
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
MHz
MHz
pF
pF
pF
pF
pF
pF
-
V
Ω
mW
2