S7017 Datasheet, PDF (3/8 Pages) Hamamatsu Corporation – CCD area image sensor

CCD area image sensor S7017 series
sElectrical and optical characteristics (Ta=25 °C, unless otherwise noted)
Parameter
Symbol Remark
Min.
Typ.
Max.
Unit
Saturation output voltage
Vsat
-
-
Fw × Sv
-
V
Full well
capacity
Vertical
Horizontal
Fw
*⁴
150
300
300
600
-
-
ke-
CCD conversion efficiency
Sv
*⁵
1.8
2.2
-
µV/e-
Dark current
(MPP mode)
+25 °C
0 °C
-70 °C
-
400
3,000
DS
*⁶
-
20
150
e-/pixel/s
-
0.0015
0.01
Readout noise
Nr
*⁷
-
6
12
e-rms
Dynamic range
Line binning
Area scanning
DR
*⁸
25,000
12,500
75,000
37,500
-
-
-
Spectral response range
λ
-
-
400 to 1,100
-
nm
Photo response non-uniformity
PRNU
*⁹
-
-
±10
%
Point defects
*¹⁰
-
-
0
Blemish
Cluster defects
-
*¹¹
-
-
0
-
Column defects
*¹²
-
-
0
*4: Large horizontal full well for line binning operation.
*5: VOD=20 V , Load resistance=22 kΩ
*6: Dark current nearly doubles for every 5 to7 °C increase in temperature.
*7: -40 °C, operating frequency is 80 kHz.
*8: DR = Fw / Nr
*9: Measured at half of the full well capacity. PRNU (%) = noise / signal × 100, noise: fixed pattern noise (peak to peak)
*10: White spots > 3 % of full well at 0 °C after Ts=1 s, Black spots > 50 % reduction in response relative to adjacent
pixels
*11: continuous 2 to 9 point defects
*12: continuous >10 point defects
s PIN connections
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
P-
NC
SS
NC
ISV
IG2V
IG1V
RG
RD
OS
OD
OG
SG
P+
TSH1
TSC1
TSC2
P2H
P1H
IG2H
IG1H
ISH
P2V
P1V
TE-cooler-
Description
Substrate (GND)
Test point (vertical input source)
Test point (vertical input gate-2)
Test point (vertical input gate-1)
Reset gate
Reset drain
Output transistor source
Output transistor drain
Output gate
Summing gate
TE-cooler+
Temperature sensor (hot side)
Temperature sensor (cool side)
Temperature sensor (cool side)
CCD horizontal register clock-2
CCD horizontal register clock-1
Test point (horizontal input gate-2)
Test point (horizontal input gate-1)
Test point (horizontal input source)
CCD vertical register clock-2
CCD vertical register clock-1
25
TG
Transfer gate
26
NC
27
NC
28
TSH2 Temperature sensor (hot side)
*13: TG is an isolation gate between vertical register and horizontal resister.
In standard operation, the same pulse of P2V should be applied to the TG.
Remark
Shorted to RD
Shorted to 0 V
Shorted to 0 V
Same timing as P2H
Shorted to 0 V
Shorted to 0 V
Shorted to RD
Same timing as P2V *¹³
3