GS81302T06 Datasheet, PDF (9/29 Pages) GSI Technology – 144Mb SigmaDDRTM-II+ Burst of 2 SRAM

GS81302T06/11/20/38E-500/450/400/350
Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table
DQ
K_n
LD
R/W
A+0
A+1
Operation
↑
1
X
Hi-Z / *
Hi-Z / *
Deselect
↑
0
0
D@K_n+1
D@K_n+1
Write
↑
0
1
Q@K_n+2
Q@K_n+3
Read
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.
2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.
4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP
and Write commands, 2.5 cycles after the command is sampled.
5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.5
cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the
state of the DQ input termination. See the Input Termination Impedance Control section for more information.
Rev: 1.03c 11/2011
9/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology