GS81302T06 Datasheet, PDF (24/29 Pages) GSI Technology – 144Mb SigmaDDRTM-II+ Burst of 2 SRAM

GS81302T06/11/20/38E-500/450/400/350
JTAG TAP Instruction Set Summary
Instruction
Code
Description
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
GSI
011
GSI Private Instruction.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
GSI
101
GSI Private Instruction.
GSI
110
GSI Private Instruction.
BYPASS
111
Places Bypass Register between TDI and TDO.
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Notes
1
1, 2
1
1
1
1
1
1
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
V_ILJ
–0.3
0.3 * V_DD
V
1
Test Port Input High Voltage
V_IHJ
0.7 * V_DD
V_DD +0.3
V
1
TMS, TCK and TDI Input Leakage Current
I_INHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
I_INLJ
–1
100
uA
3
TDO Output Leakage Current
I_OLJ
–1
1
uA
4
Test Port Output High Voltage
V_OHJ
V_DD – 0.2
—
V
5, 6
Test Port Output Low Voltage
V_OLJ
—
0.2
V
5, 7
Test Port Output CMOS High
V_OHJC
V_DD – 0.1
—
V
5, 8
Test Port Output CMOS Low
V_OLJC
—
0.1
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < V_DDn +1 V not to exceed V maximum, with a pulse width not to exceed 20% tTKC.
2. V_ILJ ≤ V_IN ≤ V_DDn
3. 0 V ≤ V_IN ≤ V_ILJn
4. Output Disable, V_OUT = 0 to V_DDn
5. The TDO output driver is served by the V_DD supply.
6. I_OHJ = –2 mA
7. I_OLJ = + 2 mA
8. I_OHJC = –100 uA
9. I_OLJC = +100 uA
Rev: 1.03c 11/2011
24/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology